1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in which both a high-breakdown-voltage MOS (Metal Oxide Semiconductor) transistor and a low-breakdown-voltage MOS transistor having different drain breakdown voltages are formed on an identical substrate, and also to a semiconductor device manufactured by this method.
2. Description of the Related Art
An integrated circuit for actuating, for example, an imaging element, an LCD (Liquid Crystal Display), or a print head (hereinafter referred to as the xe2x80x98actuation ICxe2x80x99) generally includes an actuation output module with a high-breakdown-voltage MOS transistor, which is driven by a power supply voltage of 10 or greater volts and has a high withstand voltage between a drain and a source (hereinafter may be referred to as the xe2x80x98drain breakdown voltagexe2x80x99), and a logic module with a low-breakdown-voltage MOS transistor, which is driven by a power supply voltage of several or less volts and has a low drain breakdown voltage, for controlling the actuation output module. In the description below, the MOS transistor may be simply called the transistor.
In the actuation IC, it is preferable that the high-breakdown-voltage transistor and the low-breakdown-voltage transistor are formed on an identical substrate. The simplest method of forming such transistors of different withstand voltages on an identical substrate is to separately form the respective transistors according to different processes. The method first forms one of the high-breakdown-voltage transistor and the low-breakdown-voltage transistor on a substrate, and subsequently forms the other transistor on the same substrate.
The method of separately forming the high-breakdown-voltage transistor and the low-breakdown-voltage transistor, however, significantly increases the total number of manufacturing steps, thus worsening the production efficiency and increasing the manufacturing cost.
There is accordingly a demand for efficiently forming both a high-breakdown-voltage transistor and a low-breakdown-voltage transistor on an identical substrate without damaging the characteristics of the respective transistors.
The object of the present invention is thus to solve the drawback of the prior art technique discussed above and to provide a technique of efficiently forming both a high-breakdown-voltage transistor and a low-breakdown-voltage transistor on an identical substrate without damaging the characteristics of the respective transistors.
In order to attain at least part of the above and the other related objects, the present invention is directed to a method of manufacturing a semiconductor device, in which both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor having different drain breakdown voltages are formed on an identical semiconductor substrate. The manufacturing method includes the steps of: (a) forming a gate electrode on a first dielectric film created above the substrate; (b) forming a side wall on a side face of the gate electrode; and (c) implanting an impurity to define a drain area and a source area. The step (b) has the sub-steps of: (b-1) creating a second dielectric film on surface of the substrate including the gate electrode; (b-2) forming a first mask, which covers a specific area corresponding to the high-breakdown-voltage MOS transistor; and (b-3) using the first mask and etching the second dielectric film, which is located on a certain area corresponding to the low-breakdown-voltage MOS transistor, out of the dielectric films created on the substrate, so as to form the side wall of the second dielectric film on the side face of the gate electrode in the low-breakdown-voltage MOS transistor.
The manufacturing method of the present invention enables both the high-breakdown-voltage MOS transistor and the low-breakdown-voltage MOS transistor to be efficiently formed on an identical substrate. In the process of forming the side wall, the specific area corresponding to the high-breakdown-voltage MOS transistor is covered with the first mask. Such coverage effectively prevents the second dielectric film in a neighborhood of the gate electrode in the high-breakdown-voltage MOS transistor from being undesirably thinned even in the case of over-etching to form the side wall in the low-breakdown-voltage MOS transistor. This effectively prevents the impurity from being implanted into a lower layer of the first dielectric film in the vicinity of the gate electrode in the high-breakdown-voltage MOS transistor to define the drain area and the source area or to silicidate the surface area of the lower layer. The arrangement does not cause a decrease in drain breakdown voltage nor damages the breakdown voltage characteristics of the high-breakdown-voltage MOS transistor.
In accordance with one preferable application of the manufacturing method of the invention, the step (c) has the sub-steps of: (c-1) forming a second mask that keeps open at least a drain-source forming region in the high-breakdown-voltage MOS transistor, which is expected to form the drain area and the source area, and the gate electrode but covers at least an offset forming region in the high-breakdown-voltage MOS transistor, which is expected to form an offset area between the gate electrode and either one of the drain area and the source area; (c-2) using the second mask and etching off at least the first and the second dielectric films located on the drain-source forming region and the second dielectric film located on the gate electrode, out of the dielectric films created on the substrate; and (c-3) continuously using the second mask and implanting the impurity into at least the drain-source forming region and the gate electrode.
In this preferable application, the second mask is used to prevent the impurity from being implanted into the lower layer of the first dielectric film in the vicinity of the gate electrode in the high-breakdown-voltage MOS transistor in the process of impurity implantation.
The procedure of this application uses the first mask and etches off the first dielectric film and the second dielectric film on the drain-source forming region in the high-breakdown-voltage MOS transistor. The procedure does not remove the first mask but continuously uses the same mask and implants the impurity into the drain-source forming region. This arrangement effectively prevents a positional shift of the mask and ensures accurate implantation of the impurity into the drain-source forming region.
In the above application, it is preferable that the sub-step (c-1) forms the second mask that covers an element forming region in the low-breakdown-voltage MOS transistor, which is expected to form an element, in addition to the offset forming region. The step (c) further has the sub-steps of (c-4) forming a third mask, which keeps open at least the element forming region in the low-breakdown-voltage MOS transistor; and (c-5) using the third mask and implanting the impurity into at least the element forming region.
The second mask, which covers the element forming region in the low-breakdown-voltage MOS transistor, is used in the process of etching off the first and the second dielectric films on the drain-source forming region in the high-breakdown-voltage MOS transistor. The element forming region in the low-breakdown-voltage MOS transistor is thus not affected by the etching. There is accordingly no possibility that part of the side wall is etched off in the low-breakdown-voltage MOS transistor.
In the above application, it is preferable that the manufacturing method further has the step of: (d) forming a metal film on the gate electrode, the drain area, and the source area and carrying out heat treatment, so that at least part of semiconductor layers constructing the gate electrode, the drain area, and the source area is fused to a metal of the metal film and is thereby silicidated.
On conclusion of the step (c), in the high-breakdown-voltage MOS transistor, the first dielectric film in the vicinity of the gate electrode is covered with and protected by the second dielectric film. The subsequent silicidation process of the step (d) accordingly does not silicidate the semiconductor in the lower layer of the first dielectric film in the vicinity of the gate electrode. This arrangement effectively prevents a decrease in drain breakdown voltage due to silicidation of the semiconductor in the lower layer, thus not damaging the voltage breakdown characteristics of the high-breakdown-voltage MOS transistor.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiment with the accompanying drawings.